This position is for a FPGA Verification engineer to work in the
Electronics Center for the Raytheon Intelligence & Space (RIS)
Business Unit. The person hired for this position will develop
verification environment utilizing UVM, run randomized and direct
testing to achieve closure on functional and code coverage, trace
requirement, performs reviews and audits on the simulation test
procedures and test environment. Maintain the desire to stay
current in the continuously developing field and to expand
knowledge base and skills in FPGA design, verification, and digital
* Minimum 8 years of experience in digital hardware FPGA design
* Expertise in HVL and HDL (SystemVerilog, Verilog).
* Advanced knowledge of HVL methodology (UVM/OVM/VMM).
* Solid verification skills in problem solving, constrained
random testing, and debugging.
* Experience in scripting languages such as Python.
* Experience with SystemVerilog Assertion (SVA).
* A great teammate with excellent communication skills and the
desire to take on diverse challenges.
* U.S. Citizenship status is required as this position will
require the ability to access US only data systems.
* Clearance required within 1st year AND role requires access to
US only data
* U.S. Citizenship status is required as this position will need
a U.S. Security Clearance within 1 year of start date.
* Designing for space application
* Experience with formal verification
* Digital signal processing experience
* Experience with DDR3/4, PCIe, sRIO, SPI, SpW interfaces
* Designing latest Xilinx, Altera, Microsemi FPGAs
* Programming experience in C/C++
* Algorithm verification experience using Matlab/Simulink
* Bachelor of Science in Electrical Engineering
* Master of Science in Electrical Engineering
Raytheon is an Equal Opportunity/Affirmative Action employer.
All qualified applicants will receive consideration for employment
without regard to race, color, religion, creed, sex, sexual
orientation, gender orientation, gender identity, national origin,
disability, or protected Veteran status.